Course Staff

	Name	E-mail	Office Hour(s)
Instructor	Justin Hsia	jhsia@cs	Wed 12:30 - 1:30 pm (Zoom) Fri 8:30 - 9:30 am (Zoom)
Teaching Assistants	Andrea Dang	ald8888	Mon 4:00 - 5:00 (CSE 003)
	Ethan Coffey	coffee3	Mon 3:00 - 4:00 (Hybrid: CSE 003, Zoom)
	Hafsa Khan	hafsa	Tue 1:00 - 2:00 pm (CSE 003)
	Jason Li	lzw365	Tue 3:30 - 4:30 pm (Zoom)
	Tilboon Elberier	elberb	Wed 12:00 - 1:00 pm (Hybrid: CSE 003, Zoom)
	Yui Suzuki	ysuzuki1	Fri 12:30 - 1:30 pm (CSE 003)

Scheduled Sections

	Location	Times	Staff Members
Lecture	BAG 261	Tu 11:30 am - 12:50 pm	Justin
Lab Wed	CSE 003	W 2:30 - 5:20 pm	Ethan, Jason, Yui
Lab Thu	CSE 003	Th 2:30 - 5:20 pm	Andrea, Hafsa, Tilboon

Notice: If you forget when your scheduled demonstration time slot is, please see the comments on the "Lab Demo Slot" assignment.

Class Schedule

Week	Lecture	Reading	Assignments
1	01/04: Combinational Logic (PDF) (ink)	1.0-1.4 2.0-2.7	Read the Lab Report Guide. Fill out the Pre-course Survey. Due: 01/07
2	01/11: Verilog Basics (PDF) (ink)	2.9-2.10	Lab 1 (& 2): Intro to Verilog and Digital Components Due: 01/19
3	01/18: Karnaugh Maps (PDF) (ink)	2.11, 2.12, 2.14	Lab 3: Digital Design using FPGAs Due: 01/26
4	01/25: Sequential logic (PDF) (ink)	5.0-5.4.4	Lab 4: High-Level Verilog Due: 02/02
5	02/01: Finite state machines (FSMs) (PDF) (ink) Quiz 1 (solutions)	6.0-6.4	Lab 5: Sequential Logic Due: 02/09
6	02/08: FSM Design, Multiplexors, Adders (PDF) (ink)	3.0-3.3.3, 3.3.5	Lab 6: Communicating Sequential Logic Due: 02/16
7	02/15: Encoders, Decoders, Registers, Counters (PDF) (ink)	4.0-4.1.1, 4.2-4.3	Lab 7: Useful Components Due: 02/23
8	02/22: Project Tips (PDF) (ink) Quiz 2 (solutions)	5.8-5.9	Lab 8: Final Project
9	03/01: Computer Components, FPGAs (PDF) (ink)	B.6	Check-in: 03/02 - 03/03
10	03/08: Quiz 3 (solutions)		Due: 03/11 @ 11:59 pm

Lectures will have both a "pre" version (PDF) and a "post" version with annotations (ink).

Course Materials

	This Canvas site will have lecture slides and lab assignments posted in the Files section as we go.
	Your lab materials will be submitted to and graded on Gradescope. Quizzes will also be taken on the Gradescope platform.
	We will be using Ed Discussion for our Discussion Board. Announcements will also be made here, so make sure you are enrolled.
	In lab, we will be using the DE1-SoC Development Kit and our class boards have been generously donated by Altera, Inc.
	The optional text is the third edition of Brown and Vranesic's Fundamentals of Digital Logic with Verilog Design book ("B&V"), ISBN 9870073380544.
	Videos on the course content are available thanks to Georg Selig, who ran an online version of this course. Viewing these videos is optional, but they may be useful for reviewing some of the lecture content or use of important tools for lab.

Grading

Assignment	% of Grade
Labs (7 labs and a project)	66%
Quiz 1 (02/01 in lecture)	10%
Quiz 2 (02/22 in lecture)	10%
Quiz 3 (03/08 in lecture)	14%

Late Policy

Labs are a combination of a submitted lab report and an in-person lab demo. Lateness for these portions are considered independently.

Lateness	< 24 hr	< 48 hr	< 72 hr	≥ 72 hr
Penalty	10%	30%	60%	100%

Resources

Lab Report Writing Guide: (pdf)
Quartus 17.0 Install Files: (dir) -- if you would like to work on labs on your own machine
Quartus Tutorial: (pdf)
SystemVerilog Quick Reference Card: (pdf)
SystemVerilog Tutorial: (pdf)
SystemVerilog Common Issues: (Google Doc)
ModelSim Usage Guide: (Google Doc)
LED Matrix Board: (Tutorial, Files) -- if you choose to use for your project
Other DE1-SoC Peripherals: (html) -- if you choose to use for your project

Other Policies

Student Conduct and Academic Integrity

The University of Washington Student Conduct Code (WAC 478-121) defines prohibited academic and behavioral conduct and describes how the University holds students accountable as they pursue their academic goals. Allegations of misconduct by students may be referred to the appropriate campus office for investigation and resolution. More information can be found online at https://www.washington.edu/studentconduct/.

The University takes academic integrity very seriously. Behaving with integrity is part of our responsibility to our shared learning community. If you’re uncertain about if something is academic misconduct, ask me. I am willing to discuss questions you might have. For more information, you may consult the school's Academic Misconduct Policy.

Disability Resources

Your experience in this class is important to me. It is the policy and practice of the University of Washington to create inclusive and accessible learning environments consistent with federal and state law. If you have already established accommodations with Disability Resources for Students (DRS), please activate your accommodations via myDRS so we can discuss how they will be implemented in this course.

If you have not yet established services through DRS, but have a temporary health condition or permanent disability that requires accommodations (conditions include but not limited to; mental health, attention-related, learning, vision, hearing, physical or health impacts), contact DRS directly to set up an Access Plan. DRS facilitates the interactive process that establishes reasonable accommodations. Contact DRS at disability.uw.edu.

Religious Accommodations

Washington state law requires that UW develop a policy for accommodation of student absences or significant hardship due to reasons of faith or conscience, or for organized religious activities. The UW’s policy, including more information about how to request an accommodation, is available at Religious Accommodations Policy. Accommodations must be requested within the first two weeks of this course using the Religious Accommodations Request form.

CSE369 Wi22: Introduction To Digital Design