Course Staff

	Name	E-mail	Name	E-mail
Instructor	Justin Hsia	jhsia@cs
Teaching Assistants	Caitlyn Rawlings	crawlin	Jacob Christy	jacobc03@cs
	Nik Smith	nsmith12	Shivank Shekhar	shiv76
	Srivatshan Sakthinarayanan	srisakth

Course questions should be brought to office hours or posted on the course discussion board; questions will not be answered through emails. Please limit emailing the course staff to personal issues and other extenuating circumstances (see bottom of this page).

Scheduled Sections

Location

Times

Staff Members

Lecture

ECE 037

Tu 1:30 - 2:50 pm

Justin + TAs

Labs

CSE 003 / Zoom

W 2:30 - 5:20 pm
Th 2:30 - 5:20 pm

Caitlyn, Sri, Jacob
Nik, Shivank, Jacob

Other Office Hours

CSE 003 / Zoom

(H) = hybrid
(P) = in-person
(Z) = Zoom

M 3:30 - 4:30 pm (H)
Tu 3:00 - 5:00 pm (H)
W 10:00 - 11:00 am (Z)
F 2:30 - 4:30 pm (H)

See Zoom tab or Canvas Calendar.

Caitlyn, Shivank
Sri, Shivank, Nik
Justin
Jacob, Nik, Caitlyn

Notice: If you forget when your scheduled demonstration time slot is, please see the comments on the "Lab Demo Slot" assignment.

Class Schedule

Week	Lecture	Reading	Assignments
1	03/28: Combinational Logic (PDF) (ink)	1.0-1.4 2.0-2.7	Read the Lab Report Guide. Fill out the Pre-course Survey. Due: 03/31
2	04/04: Verilog Basics (PDF) (ink)	2.9-2.10	Lab 1 (& 2): Intro to Verilog and Digital Components Due: 04/12
3	04/11: Karnaugh Maps (PDF) (ink)	2.11, 2.12, 2.14	Lab 3: Digital Design using FPGAs Due: 04/19
4	04/18: Sequential logic (PDF) (ink)	5.0-5.4.4	Lab 4: High-Level Verilog Due: 04/26
5	04/25: Finite state machines (FSMs) (PDF) (ink) Quiz 1 (solutions)	6.0-6.4	Lab 5: Sequential Logic Due: 05/03
6	05/02: FSM Design, Multiplexors, Adders (PDF) (ink)	3.0-3.3.3, 3.3.5	Lab 6: Communicating Sequential Logic Due: 05/10
7	05/09: Encoders, Decoders, Registers, Counters (PDF) (ink)	4.0-4.1.1, 4.2-4.3	Lab 7: Useful Components Due: 05/17
8	05/16: Project Tips (PDF) (ink) Quiz 2 (solutions)	5.8-5.9	Lab 8: Final Project
9	05/23: Computer Components, FPGAs (PDF) (ink)	B.6	Check-in: 05/24 - 05/25
10	05/30: Quiz 3 (solutions)		Due: 06/02 @ 11:59 pm

Lectures will have both a "pre" version (PDF) and a "post" version with annotations (ink).

Course Materials

	This Canvas site will have lecture slides and lab assignments posted in the Files section as we go.
	Your lab materials will be submitted to and graded on Gradescope. Quizzes will be taken in-person during lecture and then scanned and uploaded to Gradescope for grading.
	We will be using Ed Discussion for our Discussion Board. Announcements will also be made here, so make sure you are enrolled.
	In lab, we will be using the DE1-SoC Development Kit and our class boards have been generously donated by Altera, Inc.
	The optional text is the third edition of Brown and Vranesic's Fundamentals of Digital Logic with Verilog Design book ("B&V"), ISBN 9870073380544.
	Videos on the course content are available thanks to Georg Selig, who ran an online version of this course. Viewing these videos is optional, but they may be useful for reviewing some of the lecture content or use of important tools for lab.

Grading

Assignment	% of Grade
Labs (7 labs and a project)	66%
Quiz 1 (04/25 in lecture)	10%
Quiz 2 (05/16 in lecture)	10%
Quiz 3 (05/30 in lecture)	14%

We will use a straight-scale grading system where 95% → 4.0 and 65% → 2.0 and everything in-between is linearly interpolated. Extra credit opportunities will be factored directly into your grades (i.e., 1 extra credit point = 1 normal point).

Lab Policies

Labs are a combination of a lab report and a lab demo, which are graded independently:

The lab reports are submitted to Gradescope and are due Wednesday @ 2:30 pm, which is before you demo with a TA. This is to encourage you to do all of your testing and data collection as you develop your lab and will prepare you for the lab demo.
- See the Lab Report Guide (linked in the Week 1 schedule above) for a sense of what you will be asked to do.
The lab demos are done synchronously with a TA, typically during your assigned 10-minute lab demo slot on Wednesday or Thursday afternoon.
- Lab demos are a chance for you to present your work and get feedback as you get more comfortable with SystemVerilog and the DE1-SoC. The TAs will also have 1-2 short questions for you to answer about the lab.
- It is possible to get a full demo score even if you do not finish the lab! Please come and present what work you did and where/how you got stuck so the TAs can give you feedback and tips for future labs.

Late Policy

Lateness applies differently to the lab reports and the lab demos:

Lab reports have lateness counted in days after the Wednesday 2:30 pm deadline.
- No lab report may be submitted more than 2 days late (i.e., final deadline is Friday @ 2:30 pm).
- You will be given 4 late day tokens for the quarter that will cancel out penalties for late submissions. Once you have exhausted your late day tokens, each remaining late day will become a 10% penalty assessed on one of your late submissions, though chosen to maximize your overall score.
Lab demos cannot be penalized but must be completed by the end of Friday each week. You are allowed to demo during office hours, but should notify the course staff ahead of time (e.g., via private post on Ed) to book a 10-minute slot.
- Unless you are submitting your lab report late, you will be expected to demo during your assigned lab demo slot each week.

Resources

Lab Report Writing Guide: (pdf)
Quartus 17.0 Install Files: (dir) -- if you would like to work on labs on your own machine
Quartus Tutorial: (pdf)
SystemVerilog Quick Reference Card: (pdf)
SystemVerilog Tutorial: (pdf)
SystemVerilog Common Issues: (Google Doc)
ModelSim Usage Guide: (Google Doc)
LED Matrix Board: (Tutorial, Files) -- if you choose to use for your project
Other DE1-SoC Peripherals: (html) -- if you choose to use for your project

Other Policies

Student Conduct and Academic Integrity

The University of Washington Student Conduct Code (WAC 478-121) defines prohibited academic and behavioral conduct and describes how the University holds students accountable as they pursue their academic goals. Allegations of misconduct by students may be referred to the appropriate campus office for investigation and resolution. More information can be found online at https://www.washington.edu/studentconduct/.

The University takes academic integrity very seriously. Behaving with integrity is part of our responsibility to our shared learning community. If you’re uncertain about if something is academic misconduct, ask me. I am willing to discuss questions you might have. For more information, you may consult the school's Academic Misconduct Policy.

Disability Resources

Your experience in this class is important to me. It is the policy and practice of the University of Washington to create inclusive and accessible learning environments consistent with federal and state law. If you have already established accommodations with Disability Resources for Students (DRS), please activate your accommodations via myDRS so we can discuss how they will be implemented in this course.

If you have not yet established services through DRS, but have a temporary health condition or permanent disability that requires accommodations (conditions include but not limited to; mental health, attention-related, learning, vision, hearing, physical or health impacts), contact DRS directly to set up an Access Plan. DRS facilitates the interactive process that establishes reasonable accommodations. Contact DRS at disability.uw.edu.

Religious Accommodations

Washington state law requires that UW develop a policy for accommodation of student absences or significant hardship due to reasons of faith or conscience, or for organized religious activities. The UW’s policy, including more information about how to request an accommodation, is available at Religious Accommodations Policy. Accommodations must be requested within the first two weeks of this course using the Religious Accommodations Request form.

Extenuating Circumstances

We recognize that our students come from varied backgrounds and can have widely-varying circumstances. If you have any unforeseen or extenuating circumstances that arise during the course, please do not hesitate to contact the instructor in office hours, via email, or private Ed Discussion post to discuss your situation. The sooner we are made aware, the more easily these situations can be resolved. Extenuating circumstances include work-school balance, familial responsibilities, military duties, unexpected travel, or anything else beyond your control that may negatively impact your performance in the class.

Additionally, if at any point you are made to feel uncomfortable, disrespected, or excluded by a staff member or fellow student, please report the incident so that we may address the issue and maintain a supportive and inclusive learning environment. Should you feel uncomfortable bringing up an issue with a staff member directly, you may consider sending anonymous feedback or contacting the Office of the Ombud.

CSE 369 Sp23: Introduction To Digital Design